1. Field of Invention
This invention is related to a semiconductor process, and particularly to a method of fabricating a semiconductor device structure.
2. Description of Related Art
MOS is a basic structure widely applied to various semiconductor devices, such as memory devices, image sensors and display devices. The traditional MOS transistor is difficult to scale down due to the limitation of the fabricating process, and strained source/drain is therefore developed. In the strained source/drain process, a single etching process is performed to form recesses beside the gate electrode, and a semiconductor compound having a lattice parameter different from that of the material of the substrate is grown in the recesses.
However, since a longer time is required to etch the thick gate dielectric layer, the gate dielectric layer under the gate electrode may be etched in the lateral direction. Therefore, an undercut is observed in the gate dielectric layer under the gate electrode. As a result, the semiconductor compound may contact with the gate electrode to cause a short circuit and the process margin can be decreased.